compiler/tests/fixtures/runtime/atomic-tick-firmware/main.ldn

1--  Prototype 5's firmware/tick: time from an interrupt, with one writer,
2--  the handler, and any number of readers.  The writer needs no
3--  read-modify-write, which Cortex-M0 has not: sole_add is a relaxed load
4--  and a release store, and a reader's load acquires.  A runtime fixture
5--  places no vector, so the program is the writer here and counts where
6--  it would wait; environments/cortex-m/probes/fibre-capacity.ldn runs the
7--  same writer as SysTick's handler on Cortex-M0.
8import core/atomic
9
10mut ticks: atomic.cell(u32) = zeroed
11
12count_tick: () -> none =
13    _ = atomic.sole_add(addr ticks, 1)
14end count_tick
15
16now_ticks: () -> (count: u32) =
17    count = atomic.load(addr ticks)
18end now_ticks
19
20--  Wait for three ticks after the first reading, as a fibre waiting on the
21--  clock does, with a bound so that a count that never moves fails.
22public main: () -> (code: i32) =
23    code = 1
24    first: u32 = now_ticks()
25    mut seen: u32 = first
26    mut waits: u32 = 0
27    while seen - first < 3 and waits < 1000 do
28        count_tick()
29        seen = now_ticks()
30        inc waits
31    end while
32    if seen - first == 3 and waits == 3 then
33        code = 42
34    end if
35end main