compiler/tests/fixtures/positive/library-platform-riscv-hazard3/main.ldn

1--  Hazard3's interrupt controller (D687): an IRQ enabled in meiea and
2--  forced pending through meifa, then the core's external line opened in
3--  mie, which the compiler's meinext dispatch then serves at slot 16 + IRQ.
4import platform/riscv
5import platform/riscv/hazard3
6
7public raise_irq: (irq: u32) -> none =
8    hazard3.enable_irq(irq)
9    hazard3.force_irq(irq)
10    riscv.enable_lines(0x800)
11end raise_irq
12
13public lower_irq: (irq: u32) -> none =
14    hazard3.clear_forced_irq(irq)
15    hazard3.disable_irq(irq)
16end lower_irq